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PIC32MX3XX/4XX
9.0
PREFETCH CACHE
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1 Features
? 16 Fully Associative Lockable Cache Lines
Cache” (DS61119) of the “PIC32MX
Family Reference Manual” , which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
“Memory Organization” in this data
sheet for device-specific register and bit
information.
?
?
?
?
?
?
?
16-byte Cache Lines
Up to four Cache Lines Allocated to Data
Two Cache Lines with Address Mask to hold
repeated instructions
Pseudo LRU replacement policy
All Cache Lines are software writable
16-byte parallel memory fetch
Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
CTRL
FSM
Bus Control
Cache Control
Prefetch Control
Tag Logic
Cache
CTRL
Cache Line
Hit LRU
Miss LRU
Hit Logic
Line
Address
Encode
RDATA
CTRL
? 2010 Microchip Technology Inc.
Prefetch
PFM
Prefetch
RDATA
DS61143G-page 95
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